1. Field of the Invention
The present invention relates in general to integrated circuits, and more particularly to memory arrays in integrated circuits. Still more particularly, the present invention relates to a method for stress testing a memory array.
2. Description of the Prior Art
Stress testing of memory arrays is typically accomplished by applying an overvoltage to the gates of the transistors in the array. To perform this test, it is typical to apply the overvoltage to all of the bit and complementary bit lines, and then sequentially activate each word line in the memory. In this manner, a stress voltage is applied to every cell in the array.
This method of stress testing a memory array has several problems. First, the amount of time available to stress a memory cell is limited to the amount of time a word line is activated. As each of the word lines are sequentially activated, a memory cell is stressed for only the amount of time its corresponding word line is activated.
Second, if latent defects exist in the memory array, this method of stress testing may not detect all the defects. This is due to charge leakage through a marginal defect. Once the memory cell has stored the overvoltage, current leakage may occur and lower the voltage stored in the cell. Although some of the lost charge can be replaced by current flowing through the load element, the amount of replaced charge may be less than the charge lost. This is especially true in low power memory cells because the load resistor is very large, typically a teraohm, so very little current will flow through the resistor. Consequently, the voltage in the memory cell is not maintained at the stress level for the proper amount of time, and marginal cells may survive the stress test. This allows latent defects in the memory cell to go undetected, resulting in the production of marginal memory arrays.
Therefore, it would be desirable to provide a method for stress testing a memory array where the memory cells are maintained at the stress voltage level for the proper amount of time. It is also desirable that such a method not increase the complexity of the fabrication of integrated circuit.